LPTA_EN=DISABLED, TOP=KEEP_ON, DP_EN=SMART_PMIC_ENABLED, LPCALB_EN=DISABLED, SRTC_ENV=DISABLED, LPCALB_VAL=ADD_0_PER_32768_TICKS, SRTC_INV_EN=KEEP_VALID, MC_ENV=DISABLED
SNVS_LP Control Register
| SRTC_ENV | Secure Real Time Counter Enabled and Valid When set, the SRTC becomes operational 0 (DISABLED): SRTC is disabled or invalid. 1 (ENABLED): SRTC is enabled and valid. |
| LPTA_EN | LP Time Alarm Enable When set, the SNVS functional interrupt is asserted if the LP Time Alarm Register is equal to the 32 MSBs of the secure real time counter 0 (DISABLED): LP time alarm interrupt is disabled. 1 (ENABLED): LP time alarm interrupt is enabled. |
| MC_ENV | Monotonic Counter Enabled and Valid When set, the MC can be incremented (by write transaction to the LPSMCMR or LPSMCLR) 0 (DISABLED): MC is disabled or invalid. 1 (ENABLED): MC is enabled and valid. |
| LPWUI_EN | LP Wake-Up Interrupt Enable This interrupt line should be connected to the external pin and is intended to inform the external chip about an SNVS_LP event (MC rollover, SRTC rollover, or time alarm ) |
| SRTC_INV_EN | If this bit is 1, in the case of a security violation the SRTC stops counting and the SRTC is invalidated (SRTC_ENV bit is cleared) 0 (KEEP_VALID): SRTC stays valid in the case of security violation (other than a software violation (HPSVSR[SW_LPSV] = 1 or HPCOMR[SW_LPSV] = 1)). 1 (INVALIDATE): SRTC is invalidated in the case of security violation. |
| DP_EN | Dumb PMIC Enabled When set, software can control the system power 0 (SMART_PMIC_ENABLED): Smart PMIC enabled. 1 (DUMB_PMIC_ENABLED): Dumb PMIC enabled. |
| TOP | Turn off System Power Asserting this bit causes a signal to be sent to the Power Management IC to turn off the system power 0 (KEEP_ON): Leave system power on. 1 (TURN_OFF): Turn off system power. |
| LVD_EN | Digital Low-Voltage Event Enable By default the detection of a low-voltage event does not cause the pmic_en_b signal to be asserted |
| LPCALB_EN | LP Calibration Enable When set, enables the SRTC calibration mechanism 0 (DISABLED): SRTC Time calibration is disabled. 1 (ENABLED): SRTC Time calibration is enabled. |
| LPCALB_VAL | LP Calibration Value Defines signed calibration value for SRTC 0 (ADD_0_PER_32768_TICKS): +0 counts per each 32768 ticks of the counter clock 1 (ADD_1_PER_32768_TICKS): +1 counts per each 32768 ticks of the counter clock 2 (ADD_2_PER_32768_TICKS): +2 counts per each 32768 ticks of the counter clock 15 (ADD_15_PER_32768_TICKS): +15 counts per each 32768 ticks of the counter clock 16 (SUB_16_PER_32768_TICKS): -16 counts per each 32768 ticks of the counter clock 17 (SUB_15_PER_32768_TICKS): -15 counts per each 32768 ticks of the counter clock 30 (SUB_2_PER_32768_TICKS): -2 counts per each 32768 ticks of the counter clock 31 (SUB_1_PER_32768_TICKS): -1 counts per each 32768 ticks of the counter clock |
| BTN_PRESS_TIME | This field configures the button press time out values for the PMIC Logic |
| DEBOUNCE | This field configures the amount of debounce time for the BTN input signal |
| ON_TIME | The ON_TIME field is used to configure the period of time after BTN is asserted before pmic_en_b is asserted to turn on the SoC power |
| PK_EN | PMIC On Request Enable The value written to PK_EN will be asserted on output signal snvs_lp_pk_en |
| PK_OVERRIDE | PMIC On Request Override The value written to PK_OVERRIDE will be asserted on output signal snvs_lp_pk_override |
| GPR_Z_DIS | General Purpose Registers Zeroization Disable |